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Why are parentheses (or braces) needed in this minimal Makefile?

Ask Time:2018-06-08T22:08:28         Author:lissachen

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I am baffled why I need to echo $(VAR1) or ${VAR1} to get the output "abcd" in this Makefile:

VAR1=abcd

myTarget:
        @echo $VAR1

all: myTarget

.PHONY: all

Instead, make will echo $V (which is the empty string), and then "AR1", which is my output.

I know in bash, echo $VAR1 works to get "abcd", and my understanding is that the indented part of the code is run in bash. I'm using GNU Make 3.81.

Author:lissachen,eproduced under the CC 4.0 BY-SA copyright license with a link to the original source and this disclaimer.
Link to original article:https://stackoverflow.com/questions/50762490/why-are-parentheses-or-braces-needed-in-this-minimal-makefile
MadScientist :

It's needed because that's the syntax make uses to reference variables. For instance see the GNU make manual, or even the POSIX standard definition of make.\n\nNote that makefiles are not shell scripts, and don't have the same syntax as shell scripts. Makefiles do contain shell scripts (or at least shell commands), in recipes.\n\nBy setting the variable:\n\nVAR1 = abcd\n\n\nin your makefile you're creating a make variable, not a shell variable.\n\nA recipe (command indented by a TAB) is first parsed by make and all the make variable references are expanded. Then the result of that expansion is passed to the shell. Since you want to refer to a make variable in your recipe, you have to use the make variable reference syntax.",
2018-06-08T18:18:44
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